CPCI-DA16

CPCI 16 channel, 16-Bit D/A

16-channel, 16-bit, 10 μsec D/A converters with buffered outputs
3U high Compact PCI module
Two banks of 256Kbyte SRAM for waveform tables
±10 V outputs
Buffered outputs with options for 40 or 250 mA
Automated state machine and buffer RAM to minimize impact to the host
High current outputs suitable for control applications
Front panel I/O accessible
Selectable external or internal power supply input option

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CPCI-DA16

CPCI 16 channel, 16-Bit D/A

Product Details

16-channel, 16-bit, 10 μsec D/A converters with buffered outputs
3U high Compact PCI module
Two banks of 256Kbyte SRAM for waveform tables
±10 V outputs
Buffered outputs with options for 40 or 250 mA
Automated state machine and buffer RAM to minimize impact to the host
High current outputs suitable for control applications
Front panel I/O accessible
Selectable external or internal power supply input option

The CPCI-DA16 is a slave Digital to Analog board that is managed by the host processor on the CPCI bus. The card contains a state machine that performs most of the work of outputting data, in order to minimize the impact to the HOST system. The SRAM can also be used as a waveform table for output control.

Available Software Drivers and Software Tools:

The CPCI-DA16 is supported by ALPHI Technology under Windows NT by a Board Support Package which is supplied with the card.

Applications:

The CPCI-ADDA supports P.I.D. loop closure frame rates of up to 4 KHz per channel. The CPCI host can download gain and setpoint changes on the fly. The CPCI host can read back the current values for feedback, error, set-point, and output drive on each channel.

The local DSP processor can be used for data processing such as digital filters and FFTs. The DSP can also be used as a waveform generator to drive the 16-bit DAC.

PCI Bus Controller Features:

- - Uses the AMCC S5935 PCI controller
  - PCI 2.1 compliant master/slave
  - 132 Mbytes/sec transfer rate
  - Supports Windows NT service pack 2 & 3
  - PCI bus operation DC to 33 MHz
  - Four definable pass-through data channels
  - Two 32-byte internal FIFOs with DMA
  - Four mailbox registers with byte-level status and data strobe/interrupts
  - Direct PCI and add-on interrupt pins
  - Serial nvRAM interface or byte-wide nonvolatile memory interface
  - Performs Big Endian/Little Endian conversion

TI DAC712UB D/A Specifications:

- - 16-channel, 16-bit D/A
  - Voltage output ±10 V
  - Binary 2’s Complement Format
  - DAC712 has a precision +10V temperature-compensated voltage reference
  - The digital interface is fast, 60ns minimum write pulse width, is double-buffered, and has a CLEAR function that resets the analog output to bipolar zero.
  - GAIN and OFFSET adjustment inputs are arranged so that they can be easily trimmed by external D/A converters as well as by potentiometers.
  - The DAC712 is specified at power supply voltages of ±12V and ±15V.

Operating Environment:

- - Operating temperature:
    - Commercial: 0 to +70 ºC
    - Optional: -25 ºC to +80 ºC
  - Non-operating: -40 ºC to +85 ºC
  - Airflow requirement – 5 CFM
  - Humidity – 5 to 90% (non-condensing)
  - Altitude – 0 to 10,000 feet

Mechanical Environment:

- Size – 3U CPCI module (100mm x 160mm)
- Power – 1.5 watt
- Vibration – 0.5G, 20-2000 Hz random
- Shock – 20G, 11 msec, ½ sine
- Weight – TBD
- MTBF – >250,000 hours

CPCI-DA16-1
3U compact PCI with 16 16-bit D/A with 40 mA output

CPCI-DA16-2
3U compact PCI with 16 16-bit D/A with 250 mA output

Optional Accessories:
CBL-SCSI-50
50-pin SCSI cable

TB-50
50-pin terminal block with cable

Data Sheet – Link Here

User Manual – Link Here

16-channel, 16-bit, 10 μsec D/A converters with buffered outputs
3U high Compact PCI module
Two banks of 256Kbyte SRAM for waveform tables
±10 V outputs
Buffered outputs with options for 40 or 250 mA
Automated state machine and buffer RAM to minimize impact to the host
High current outputs suitable for control applications
Front panel I/O accessible
Selectable external or internal power supply input option

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical Interface

PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)

PCI Express Switch

PI7C9X2G312GP (Pericom)

PCI Express to PCI Bridge

XIO2001 (Texas Instruments)

User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-Flash

MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage

DDR3 RAM

2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit

Board Configuration Controller

LCMXO2-7000HC (Lattice)

ADC

LTC2320 -16 (Analog Devices)

DAC

AD5547BRUZ (Analog Devices)

A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

Default configured as 32 ESD-protected TTL lines
16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.

Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

Can be used as single-ended or differential I/O
FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

Each line consists of one differential RX and TX pair.
Transmission speeds of up to 3.125 Gb/s are possible.

Front I/O

Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR

P14 Rear I/O

64 pin Mezzanine Connector (Molex 71436-2864 or compatible)

P16 Rear I/O

114 pin Mezzanine Connector (Samtec – ASP-105885-01)

Power Requirements ¹⁾

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

	typical @ +12 V VPWR	typical @ +5 V VPWR
TXMC639-10R	1.1 A	2.5 A
TXMC639-11R	1.3 A	3.3 A

Temperature Range

Operating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C

MTBF ¹⁾

157 000 h to 161 000 h

Humidity

5% – 95% non-condensing

Weight

140 g

¹⁾ depends on variant, for further details see User Manual

TXMC639-10R

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O