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- Form Factor: XMC VITA 61 or VITA 42 options
- Interface: PCI Express x1 lane interface
- MIL-STD-1553 Controllers: Two dual redundant MIL-STD-1553 controllers (A/B channels)
- Multiprotocol Support: MIL-STD-1553A/B, STANAG-3838, and MIL-STD-1760
- Memory: 2MB RAM per channel
- Modes: Bus Controller, Remote Terminal with concurrent Bus Monitor
- Monitoring: IRIG-106 Chapter 10 Monitor
- RT Emulation: Emulates up to 31 RT addresses simultaneously
- Filtering: Filter based on RT address, T/R bit, sub-address
- Coupling: Transformer coupled
- IRIG-B Input: IRIG-B digital input
- Digital I/O: 16 digital discrete I/O (TTL Levels)
- Digital Outputs: 2 digital outputs
- Form Factor: Single-wide XMC (2.92” x 5.87”)
- MIL-STD-1553 Controller: 1 or 2 UTMC SUMMIT UT69151DX-GPC
- Modes: BC (Bus Controller), RT (Remote Terminal), BM (Bus Monitor)
- Transceivers & Transformers: On-chip transceivers, on-board transformers
- Stub Options: Long stub / Short stub
- Memory: 1 or 2 banks 128 Kbyte SRAM
- I/O: 1553 bus levels, TTL (5v) clock, front panel or rear I/O
- Interrupts: Supported
- Clock: Selectable Internal / external CLK
- Connectors: Optional front panel or rear I/O
- Options: MIL-STD-1553B, optional IRIG-B, VITA 42 compliant, 1 Lane PCIeXpress
- Form Factor: XMC module, single-wide PMC size (74mm x 149mm)
- Analog-to-Digital Conversion: 32 channels of 16-bit A/D conversion, simultaneously sampled
- Throughput: Up to 200 KSPS per channel
- Input Configuration: True differential inputs with instrumentation amplifiers per channel
- Software Programmable Gain: 1, 2, 4, 8
- Analog Input Ranges: Bipolar ±1.25 V, ±2.5 V, ±5 V, ±10 V
- Anti-alias Filtering: Programmable 2nd order analog filter
- Over-sampling and Digital Filtering: Supported
- Memory: 32 Mbits (2M x 16) dual-ported SRAM
- DMA Capabilities: Available for efficient data transfer
- Form Factor: Single-wide XMC Module
- FPGA: User Programmable Altera Cyclone IV FPGA
- 484 BGA package
- Models: EP4CE55, EP4CE75, EP4CE115
- Memory: 64 Mbyte external DDR
- I/O: 64 LVTTL I/O lines
- Reconfigurable I/O
- User configurable IO by groups of 4
- Configuration:
- On board Serial configuration device programmable via XMC bus or bit/byte blaster
- Local serial EPROM
- Clock: Internal / External clock
- Interface: PCIe X 1 Interface
- I/O Access: Front panel I/O access
- 8 Independent 16C550-class UARTs with 256-byte TX and RX FIFOs
- Up to 31.25Mbps serial data rate
- Software selectable RS-232, RS-485, and RS-422 modes in pairs
- ±15KV ESD protection
- Full or half duplex configurations
- On-board software selectable 120Ω termination
Communication Specifications:
- PCIe 2.0 Gen 1 compliant
- Automatic RTS/CTS or DTR/DSR hardware flow control
- Automatic Xon/Xoff software flow control
- RS-485 half duplex direction control with programmable turn-around delay
- Form Factor: Single wide XMC Module (2.92” x 5.87”)
- FPDP Standard: ANSI/VITA 17-1997 Front Panel Data Port standard.
- I/O Interface Options: TTL, RS-422 and Custom Mezzanine Options
- Parallel I/O: 32 Bits Parallel I/O
- FIFO: 128 KBytes deep Fifo per Module (TX / RX)
- Data Transfer: Data Transfer by On-Board DMA or PCIe Master
- Interrupts: PCIe Interrupt on Fifo Level
- Clock: Programable Clock & Selectable Internal / external CLK
- Options: VITA 42 compliant, 1 Lane PCie express, Conformal coating