CPCI-6713-ISC8

CPCI 320C6713 DSP OCTAL SERIAL CONTROLLER

  • 8 Serial channels
  • Zilog 85230 controllers
  • Mezzanine I/O module for RS-232/422/485 or user I/O
  • 3.3 / 5 Volt via PLX 9056 33/66MHz
  • TMS320C6713B, 300MHz
  • Up to 32Mbytes of SDRAM
  • 4.0 Mbit flash memory for bootstrap program

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CPCI-6713-ISC8

CPCI 320C6713 DSP OCTAL SERIAL CONTROLLER

  • 8 Serial channels
  • Zilog 85230 controllers
  • Mezzanine I/O module for RS-232/422/485 or user I/O
  • 3.3 / 5 Volt via PLX 9056 33/66MHz
  • TMS320C6713B, 300MHz
  • Up to 32Mbytes of SDRAM
  • 4.0 Mbit flash memory for bootstrap program

The new CPCI-6713-ISC8 module provides a 3U high-performance multi-protocol serial controller, supporting RS-232, RS-422/485, TTL, and user I/O configurations. It supports various communication modes, including Synchronous, Asynchronous, Bi-sync, Xon/Xoff, SDLC, and HDLC. The local DSP can be used to move data to and from the CPCI bus or provide pre-processing and custom protocol functions. Custom application software can be downloaded to the DSP via the CompactPCI bus.

The TMS320C67x DSP generation is supported by the TI eXpressDSPTM set of industry development tools, including a highly optimizing C/C++ Compiler, the Code Composer StudioTM Integrated Development Environment (IDE), JTAG-based emulation, real-time debugging, and the DSP/BIOS kernel.

DSP Specifications:

      • TMS320C6713B™ DSP @ 300 Mhz
      • 64K-Byte L2 Unified Cache/Mapped RAM
      • 192K-Byte Additional L2 Mapped RAM
      • Dual 32 bit general purpose timers
      • 16 channel EDMA ‘Enhanced DMA’
      • 16-bit Host-Port Interface (HPI)

 

CPCI Bus:

      • CPCI Bus Interface 3.3 / 5 Volt
      • PLX 9056 33/66MHz 32-bit, PCI r2.2 compliant 3.3V I/O, 5V tolerant bus interfaces

 

Debug Port:

      • JTAG emulator port
      • On board RS-232 header

 

I/O Panel Connectors:

      • Front Panel (2) X 50 pin HRS for I/O

 

Mechanical & Environmental:

    • Operating temp: 0 to +55 °C
    • Airflow requirement: 10 CFM
    • Humidity: 5 to 90% (non-cond.)
    • Altitude: 0 to 10,000 ft
    • Full size PCI card
    • Front panel I/O
    • Power: +5V 1 amp, +12V 1 amp
    • Vibration: 0.5G RMS 20-2KHz random
    • Shock: 20 G, 11 ms, ½ sine
    • Weight: 2 lbs
    • MTBF: >17200 hours

CPCI-6713-ISC8:
3U CPCI 8 channel serial controller with 320C6713 DSP

CBL-50-HRS:
Cable

TB-50-HRS:
Terminal Block

Data Sheet – Link Here

User Manual – Link Here

  • 8 Serial channels
  • Zilog 85230 controllers
  • Mezzanine I/O module for RS-232/422/485 or user I/O
  • 3.3 / 5 Volt via PLX 9056 33/66MHz
  • TMS320C6713B, 300MHz
  • Up to 32Mbytes of SDRAM
  • 4.0 Mbit flash memory for bootstrap program

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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