XMC-FPD-XXX

FPDP DIGITAL PARALLEL I/O XMC BOARD

  • Form Factor: Single wide XMC Module (2.92” x 5.87”)
  • FPDP Standard: ANSI/VITA 17-1997 Front Panel Data Port standard.
  • I/O Interface Options: TTL, RS-422 and Custom Mezzanine Options
  • Parallel I/O: 32 Bits Parallel I/O
  • FIFO: 128 KBytes deep Fifo per Module (TX / RX)
  • Data Transfer: Data Transfer by On-Board DMA or PCIe Master
  • Interrupts: PCIe Interrupt on Fifo Level
  • Clock: Programable Clock & Selectable Internal / external CLK
  • Options: VITA 42 compliant, 1 Lane PCie express, Conformal coating

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XMC-FPD-XXX

FPDP DIGITAL PARALLEL I/O XMC BOARD

  • Form Factor: Single wide XMC Module (2.92” x 5.87”)
  • FPDP Standard: ANSI/VITA 17-1997 Front Panel Data Port standard.
  • I/O Interface Options: TTL, RS-422 and Custom Mezzanine Options
  • Parallel I/O: 32 Bits Parallel I/O
  • FIFO: 128 KBytes deep Fifo per Module (TX / RX)
  • Data Transfer: Data Transfer by On-Board DMA or PCIe Master
  • Interrupts: PCIe Interrupt on Fifo Level
  • Clock: Programable Clock & Selectable Internal / external CLK
  • Options: VITA 42 compliant, 1 Lane PCie express, Conformal coating

The specifications include compliance with the ANSI/VITA 17-1997 Front Panel Data Port standard, supporting both TTL and RS-422 interfaces. The module is VITA 42 compliant, featuring a 1 Lane PCIe Express interface. Additional options include conformal coating for enhanced durability. It includes a 128 Kbyte Deep FIFO and supports DMA for efficient data transfer. The module also features All Bytes Swap capability and a programmable clock with selectable internal/external clock options. It supports data rates up to 160Mb/s and includes advanced synchronization control.

Programmable via:

  • XMC Bus VITA 42
  • 3.3V I/O, 5V tolerant bus interfaces
  • Local Bus Clock rates at 66MHz
  • Compliant PCIe Specification, r1.0a x1
  • Direct slave data transfers
  • DMA Capability
  • Up to 160Mb/s Transfer
  • DMA Transfer per FIFO Level

Features Front-End Processing:

  • ANSI/VITA 17-1997 Front Panel Data Port standard
  • Flexible Packing options: 1×32, 2×16, or 3×10 bits
  • Advanced Synchronization control features
  • Programmable Clock Generator
  • Mezzanine Options Interface: TTL, RS-422, and Custom
  • 32 Bits Parallel I/O

Features FIFO:

  • 128 KBytes deep FIFO per Module (TX/RX)
  • Data Transfer by On-Board DMA or PCIe Master
  • PCIe Interrupt on FIFO Level

Operating Environmental:

  • Operating temperature: Industrial -40°C to +85°C
  • Airflow requirement: 0.5 CFM
  • Humidity: 5 to 90% (non-cond.)
  • Altitude: 0 to 20,000 ft

Non-Operating:

  • Non-Operating temperature: -55°C to +105°C

Mechanical Environmental:

  • Size: Single wide XMC, 2.92” x 5.87”
  • Power: 1.5 watt
  • Front panel I/O
  • Vibration: 0.5G RMS, 20-2000 Hz random
  • Shock: 20G, 11 ms, ½ sine
  • Weight: TBD
  • MTBF: >250,000 hours
Ordering Information
  • Part Number: XMC-FPDP-FIU-128-I – XMC FPDP, TTL Input Module, 128K Receive Fifo, Industrial
  • Part Number: XMC-FPDP-FOU-128-I – XMC FPDP, TTL Output Module, 128K Transmit Fifo, Industrial
  • Part Number: XMC-FPDP-DIU-128-I – XMC FPDP, RS-422 Input Module, 128K Receive Fifo, Industrial
  • Part Number: XMC-FPDP-DOU-128-I – XMC FPDP, RS-422 Output Module, 128K Transmit Fifo, Industrial
  • -cc – Acrylic Conformal Coat (optional)

Data Sheet – Link Here

User Manual – Link Here

  • Form Factor: Single wide XMC Module (2.92” x 5.87”)
  • FPDP Standard: ANSI/VITA 17-1997 Front Panel Data Port standard.
  • I/O Interface Options: TTL, RS-422 and Custom Mezzanine Options
  • Parallel I/O: 32 Bits Parallel I/O
  • FIFO: 128 KBytes deep Fifo per Module (TX / RX)
  • Data Transfer: Data Transfer by On-Board DMA or PCIe Master
  • Interrupts: PCIe Interrupt on Fifo Level
  • Clock: Programable Clock & Selectable Internal / external CLK
  • Options: VITA 42 compliant, 1 Lane PCie express, Conformal coating

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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