- Form Factor: Single-wide XMC Module
- FPGA: User Programmable Altera Cyclone IV FPGA
- 484 BGA package
- Models: EP4CE55, EP4CE75, EP4CE115
- Memory: 64 Mbyte external DDR
- I/O: 64 LVTTL I/O lines
- Reconfigurable I/O
- User configurable IO by groups of 4
- Configuration:
- On board Serial configuration device programmable via XMC bus or bit/byte blaster
- Local serial EPROM
- Clock: Internal / External clock
- Interface: PCIe X 1 Interface
- I/O Access: Front panel I/O access
XMC-CIV-64LVTTL
USER RECONFIGURABLE ALTERA FPGA CYCLONE IV,64MBYTE DDR,64LV TTL
- Form Factor: Single-wide XMC Module
- FPGA: User Programmable Altera Cyclone IV FPGA
- 484 BGA package
- Models: EP4CE55, EP4CE75, EP4CE115
- Memory: 64 Mbyte external DDR
- I/O: 64 LVTTL I/O lines
- Reconfigurable I/O
- User configurable IO by groups of 4
- Configuration:
- On board Serial configuration device programmable via XMC bus or bit/byte blaster
- Local serial EPROM
- Clock: Internal / External clock
- Interface: PCIe X 1 Interface
- I/O Access: Front panel I/O access
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XMC-CIV-64LVTTL
USER RECONFIGURABLE ALTERA FPGA CYCLONE IV,64MBYTE DDR,64LV TTL
The Cyclone IV EP4C55, in a 484-FBGA package, offers a wide range of customization options. It features 64 Mbytes of DDR memory and separate logic for the XMC interface. The FPGA includes reconfigurable I/O with 64 LVTTL I/O lines, each GPIO line having independent interrupt support programmable for edge triggering. The I/O can be configured by groups of 4 or 2 pairs. The board includes an on-board serial configuration device programmable via the XMC bus or bit/byte blaster, along with a local serial EPROM. It supports both internal and external clocks and features a PCIe x1 interface. Additionally, it provides front panel I/O access and is supported by Windows and Linux drivers.
Features:
- User Programmable Altera Cyclone IV FPGA 484 BGA: EP4CE55, EP4CE75, EP4C155
- Single wide XMC Module CycloneIV Programmable via
- Bit / Byte Blaster
- Serial EPROM
- XMC Bus XMC interface
- 64 LVTL
- Optional User clock oscillator
Memory:
- 64 Mbyte external DDR
- Dual ported between the Altera and XMC bus with arbitration
I/O Level:
- 64 I/O pins externally buffered LVTTL
- Fully User programmable
- Direction programmed in Group of 4
- Change of state detection & interrupt: generated per Line on Positive or negative Edge
- Bit pattern recognition
- Cyclone IV
- Optional DMA for maximum throughput from the host
Operating Environmental:
- Operating temperature Commercial: 0 to +55 °C
- Optional: -40°C to +85°C
- Non-operating: -55°C to 95 °C
- Airflow requirement: .5 CFM
- Humidity: 5 to 90% (non-cond.)
- Altitude: 0 to 10’000 ft
Mechanical Environmental:
- Power: +3.3Volts: TBD, +12/-12Volts: TBD
- Vibration: 0.5G RMS 20-2000 Hz rand
- Direct readback of register
- Direct output control
- Pre-programmed output latch with output strobe
- Shock: 20 G, 11 ms, ½ sine
- Weight: 3 oz.
- MTBF: >250000 hours
Ordering Information:
- XMC-CIV55-64LVTTL: ALTERA EP4CE55, 64LVTTL XMC module
- XMC-CIV75-64LVTTL: ALTERA EP4CE75, 64LVTTL XMC module
- XMC-CIV115-64LVTTL: ALTERA EP4CE115, 64LVTTL XMC module
- XMC-CIVxx-64LVTTL-I: Same as above with -40 to +85 C
Optional Accessories:
- Part Number: TB-68-SCSI 68 pin terminal block and 1meter SCSI cable
- Part Number: CBL-68-SCSI 68 pin,1meter SCSI cable
- Form Factor: Single-wide XMC Module
- FPGA: User Programmable Altera Cyclone IV FPGA
- 484 BGA package
- Models: EP4CE55, EP4CE75, EP4CE115
- Memory: 64 Mbyte external DDR
- I/O: 64 LVTTL I/O lines
- Reconfigurable I/O
- User configurable IO by groups of 4
- Configuration:
- On board Serial configuration device programmable via XMC bus or bit/byte blaster
- Local serial EPROM
- Clock: Internal / External clock
- Interface: PCIe X 1 Interface
- I/O Access: Front panel I/O access
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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