- FPGA Support: XILINX Spartan IIE (XC2S50E – XC2S400E)
- Stand-Alone Capability: Can operate independently
- Memory:
- 2 Mbyte external SRAM
- Dual-ported between XILINX and IP bus with arbitration
- I/O Level:
- LVDS (Low Voltage Differential Signaling)
- LVTTL (Low Voltage Transistor-Transistor Logic)
- LPECL (Low Power Emitter-Coupled Logic)
- LVCMOS (Low Voltage Complementary Metal-Oxide-Semiconductor)
IP-SPARTAN
XILINX SPARTAN FPGA, 2MBYTE DUAL-PORTED SRAM LVDS, LVTTL, LPECL, LVCMOS, I/O DRIVERS
- FPGA Support: XILINX Spartan IIE (XC2S50E – XC2S400E)
- Stand-Alone Capability: Can operate independently
- Memory:
- 2 Mbyte external SRAM
- Dual-ported between XILINX and IP bus with arbitration
- I/O Level:
- LVDS (Low Voltage Differential Signaling)
- LVTTL (Low Voltage Transistor-Transistor Logic)
- LPECL (Low Power Emitter-Coupled Logic)
- LVCMOS (Low Voltage Complementary Metal-Oxide-Semiconductor)
Share this product
LinkedIn
IP-SPARTAN
XILINX SPARTAN FPGA, 2MBYTE DUAL-PORTED SRAM LVDS, LVTTL, LPECL, LVCMOS, I/O DRIVERS
The Xilinx FPGA IP module offers a versatile solution with options ranging from SPARTAN IIE 50K to 400K gate devices. It includes 2 Mbyte of dual-ported SRAM, providing efficient data access and manipulation. The module features separate logic for the IP interface and supports 48 selectable I/Os, allowing for flexible configuration. It is reconfigurable, supporting various I/O standards such as LVDS, LVTTL, LPECL, and LVCOMS drivers. Users can configure I/Os by groups, and the module is programmable via IP, HW-USB, or HW-PCI interfaces. Additional features include a local serial EEPROM for storing configuration data and support for both internal and external clocks. The module operates with an 8/32 MHz IP clock and is compliant with the VITA 4 standard.
Memory
- 2 Mbyte external SRAM
- Dual ported between the XILINX and IP bus with arbitration
I/O Level
- LVDS
- LVTTL
- LPECL
- LVCMOS
Programmable via
- HW-USB, HW-PCi
- Serial Eprom
- IP Bus
IP interface
- 8/32 Mhz clock
- 16 bit data
- Interrupts
- DMA
Operating: Environmental
- Operating temperature
- Commercial: 0 to +55 °C
- Optional: -25°C to +80°C
- Non-operating: -40°C to 85 °C
- Airflow requirement: CFM
- Humidity: 5 to 90% (non-cond.)
- Altitude: 0 to 10’000 ft
Mechanical: Environmental
- Size: Vita 4 Type 1 IP 1.8″ x 3.9″
- Power: watt
- Vibration: 0.5G RMS 20-2000 Hz rand
- Shock: 20 G, 11 ms, 1⁄2 sine
- Weight: tbd
- MTBF: >250000 hours
- Part Number : IP-XILINX-SPARTAN-1 50K gate SPARTAN Industry Pack module
- Part Number : IP-XILINX-SPARTAN-2 100K gateSPARTAN Industry Pack module
- Part Number : IP-XILINX-SPARTAN-3 200K gateSPARTAN Industry Pack module
- Part Number : IP-XILINX-SPARTAN-4 400K gate SPARTAN Industry Pack module
Optional Accessories
- Part Number : TB-50-HDR 50 pin terminal block and 1meter flat ribbon cable
- Part Number : CBL-50-HDR 50 pin,1meter flat ribbon cable, IDC header connector
- FPGA Support: XILINX Spartan IIE (XC2S50E – XC2S400E)
- Stand-Alone Capability: Can operate independently
- Memory:
- 2 Mbyte external SRAM
- Dual-ported between XILINX and IP bus with arbitration
- I/O Level:
- LVDS (Low Voltage Differential Signaling)
- LVTTL (Low Voltage Transistor-Transistor Logic)
- LPECL (Low Power Emitter-Coupled Logic)
- LVCMOS (Low Voltage Complementary Metal-Oxide-Semiconductor)
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
Share this product
LinkedIn
