- Up to 32 I/O pins available by groups of 8 I/O pins
- All I/O can be individually programmed as an input or output via an Altera FPGA
- Direct read-back outputs on any or all outputs
- Open drain VMOSFET VN3205 can sink up to 1.5A continuously
- Breakdown voltage of 50V
- Wide input voltage range up to +30VDC
- Very low Ron (0.3Ω) for reduced heat dissipation
- Jumper selectable pull-up resistor connected to +5VDC or external voltage source for contact closure sensing
- Jumper selectable pull-down resistor to ground for voltage contact switch sensing
- Contact voltage detect select VMOS VN3205 out01
IP-DIO-32CH
IP Programmable Digital I/O, 32 channels
- Up to 32 I/O pins available by groups of 8 I/O pins
- All I/O can be individually programmed as an input or output via an Altera FPGA
- Direct read-back outputs on any or all outputs
- Open drain VMOSFET VN3205 can sink up to 1.5A continuously
- Breakdown voltage of 50V
- Wide input voltage range up to +30VDC
- Very low Ron (0.3Ω) for reduced heat dissipation
- Jumper selectable pull-up resistor connected to +5VDC or external voltage source for contact closure sensing
- Jumper selectable pull-down resistor to ground for voltage contact switch sensing
- Contact voltage detect select VMOS VN3205 out01
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IP-DIO-32CH
IP Programmable Digital I/O, 32 channels
The IP-DIO_32CH IP board has 32 Alterabased, programmable I/O pins that support voltages of up to +30VDC. The pins can are available in groups of 8 pins. Each output can be read back. Inputs have variable thresholds, and can support contact and switched voltages. All inputs also have resistor network based variable hysterisis. All inputs can have a selectable input voltage reference – +5VDC, ground, and an external reference for other voltage inputs. A 2kbyte EEPROM is used for the board ID and user data and possible gain error for future software corrections.
More Features:
-
- External voltage reference available in01 +5 +12 LM339 ++12 +select +5 ref01 I/O CONN R1 LT1362
- Resistance selectable hysteresis on each channel VREF-12 R2 R1 & R2
- Variable threshold can be changed by resistance network
- Threshold source can be internal or external selected by jumpers
- Change of state detection can generate IP interrupt
- Integrated Altera logic for custom options
- 8 or 32 MHz clock
- 2 interrupts and 2 slave DMA IP bus lines
- VITA 4 compliant
- 2kbytes of EEPROM are used for board ID and user data storage
Applications:
-
- This is a perfect solution for control systems
Supertex VN3205 Device Specifications:
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- Drain to source breakdown voltage of +50VDC
- Continuous drain current of 1.5A
- Drain to source equivalent on resistance of 0.3Ω
- Turn on delay time of 10nsec max
- Rise time of 15nsec max
- Turn off delay time of 25nsec max
- Fall time of 25nsec max
Industry Pack Specifications:
-
- Meets ANSI/VITA 4-1995
- 8/32 MHz synchronous operation
- Supports ID, 128 byte I/O, interrupt, & 8 Mbyte memory spaces
- 2 Interrupts per module
- Two passive DMA channels are possible
- Hardware self-timed per IP module
- Triggered via system reset and software control
- Jumper or software time-out function
- 5, +/-12 volt reset-able fuse per IP
Mechanical Environmental:
-
- Size – VITA 4 compliant 1.8” x 3.9” or 46 mm x 99 mm
- Power – 1.0 watt
- Vibration – 0.5G, 20-2000 Hz rand
- Shock – 20G, 11 msec, ½ sine
- Weight – TBD
- MTBF – >250,000 hours
Operating Environment:
-
- Operating temperature:
- Commercial: 0 to +70 ºC
- Optional: -25 ºC to +80 ºC
- Non-operating: -40 ºC to +85 ºC
- Airflow requirement – 5 CFM
- Humidity – 5 to 90% (non-cond)
- Altitude – 0 to 10,000 feet
- Operating temperature:
Ordering Information:
- IP-DIO-32CH: 32-bit digital I/O Industry Pack module
- IP-DIO-32CH-I: Same as above, but operates at -40º to +85ºC
Optional Accessories:
- CBL-HDR-HRS-50: 50 pin cable, 1 meter with HRS connector
- TB-HDR-50: 50 pin terminal block
- Up to 32 I/O pins available by groups of 8 I/O pins
- All I/O can be individually programmed as an input or output via an Altera FPGA
- Direct read-back outputs on any or all outputs
- Open drain VMOSFET VN3205 can sink up to 1.5A continuously
- Breakdown voltage of 50V
- Wide input voltage range up to +30VDC
- Very low Ron (0.3Ω) for reduced heat dissipation
- Jumper selectable pull-up resistor connected to +5VDC or external voltage source for contact closure sensing
- Jumper selectable pull-down resistor to ground for voltage contact switch sensing
- Contact voltage detect select VMOS VN3205 out01
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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