- 16-bit AD977 A/D converter module
- 2 A/D modules each with 16 single-ended or 8 differential multiplexed A/D inputs for a total of 32 single-ended or 16 differential analog inputs
- Acquisition time of 100Ksps
- Programmable ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±3.3VDC, and 0-4VDC
- 64Kx18 FIFO enables burst mode or continuous sampling at lower throughput
- Channel 128K x 16 SRAM enables storage of gain, calibration, and input mode selection per input channel
- Differential inputs can be configured for single-ended, differential modes, or calibration modes (Vref or GND)
IP-AD-3216
IP 16 bit A/D converter, 2 A/D modules, 32 multiplexed input channels
- 16-bit AD977 A/D converter module
- 2 A/D modules each with 16 single-ended or 8 differential multiplexed A/D inputs for a total of 32 single-ended or 16 differential analog inputs
- Acquisition time of 100Ksps
- Programmable ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±3.3VDC, and 0-4VDC
- 64Kx18 FIFO enables burst mode or continuous sampling at lower throughput
- Channel 128K x 16 SRAM enables storage of gain, calibration, and input mode selection per input channel
- Differential inputs can be configured for single-ended, differential modes, or calibration modes (Vref or GND)
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IP-AD-3216
IP 16 bit A/D converter, 2 A/D modules, 32 multiplexed input channels
The IP-AD-3216 has four CMOS analog multiplexers that are fault protected. Each multiplexer has 8 inputs and one common output. These outputs are acquired by a four input differential multiplexer.
The differential multiplexer inputs can then be configured for single-ended, differential modes, or calibration modes. These outputs then go to a PGA where the gain can be set for 1, 2, 4, and 8.
When the acquisition is started the two A/D converters acquire the data simultaneously from the multiplexers. The data is stored in a 16-bit FIFO in an interleave matter reading group #1 (odd channel) first then group #2 (even channel). Further acquisitions before the trigger will result in the earliest data being discarded, thus maintaining the most recent data in the FIFO.
Once the trigger event is seen, no more data is discarded from the FIFO, and the acquisition proceeds until the FIFO is full. At this point, the acquisition stops, and the HOST can read the data from the IP. Interrupts can be sent to the HOST at Event and at acquisition finished.
If desired, such as for a continuous acquisition, data can be read from the FIFO while acquisition is in progress, supporting continuous streaming.
Software Support
The IP-ADM-2100-32CH is supported under Windows NT/2000 by two sample programs, which are supplied with the IP in the board support package. Both examples are designed to work with an IP-type carrier from ALPHI, such as the PCI-4IPM.
One sample program, called SnapShot, fully exercises the IP module in pre- and post-trigger modes, and displays the data to the screen. Data can be stored to a file and can be reloaded in the program at a later time.
The second program, called DrawIpAdc, operates the IP in continuous mode, and displays the data to the screen.
Full source to both HOST DSP code and the applications are provided.
More Features
- Pre-trigger and post-trigger acquisition
- Sampling clock selected from one of the following sources:
- Internal divider (IPCLK/N)
- IPSTROBE
- Trigger event selected from one of the following sources:
- Write to IP register
- IPSTROBE
- External trigger
- 8 or 32 MHz clock
- 2 interrupts and 2 slave DMA IP bus lines
- External trigger MUX 8:1
- SRAM 8, IP BUS 128K x 16, 4, 2, and 1
- MUX 8:1
- CONN 16-bit A/D AD977A
- PGA 206
- FIFO 64K x 18
- 8, 4, 2, and 1 16-bit A/D
- MUX 4:1
- Vref MUX 8:1
- MUX 8:1
- MUX I/O CONN
- VITA 4 compliant
- 32 bytes of EEPROM are used for board ID
AD977A A/D Specifications
- 16-bit, successive approximation A/D
- Fast throughput rate of 100Ksps
- Single power supply +5VDC
- Internal or external voltage references
- On-chip clock
- Analog input voltage ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±3.3VDC, and 0-4VDC
- Integral linearity error ±3LSB
- Differential linearity error -2LSB min to +3LSB max
- Full-scale error ±0.5%
- SNR 83dB
- Full power bandwidth 700KHz
- Over voltage recovery 150nsec
PGA206 Programmable Gain Amplifier Specifications
- Programmable gains of 1, 2, 4, 8
- Fast settling time 3.5 μsec to 0.01%
- FET input IB = 100pA max; eliminated IB errors due to analog multiplexer series resistance
- Input protection ±40VDC
Industry Pack Specifications
- Meets ANSI/VITA 4-1995
- 8/32 MHz synchronous operation
- Supports ID, 128 byte I/O, interrupt, & 8 Mbyte memory spaces
- 2 Interrupts per module
- Two passive DMA channels are possible
- Hardware self timed per IP module
- Triggered via system reset and software control
- Jumper or software time-out function
- 5, +/-12 volt reset-able fuse per IP
Mechanical: Environmental
- Size – VITA 4 compliant: 1.8″ x 3.9″ or 46 mm x 99 mm
- Power – 1.0 watt
- Vibration – 0.5G, 20-2000 Hz rand
- Shock – 20G, 11 msec, 1⁄2 sine
- Weight – 2 ounces
- MTBF – >250,000 hours
Operating Environment
- Operating temperature
Commercial: 0 to +70°C
Optional: -25°C to +80°C - Non-operating: -40°C to +85°C
- Airflow requirement – 5 CFM
- Humidity – 5 to 90% (non-condensing)
- Altitude – 0 to 10,000 feet
Part number: IP-AD-3216
32 channel 16 bit multiplexed A/D Industry Pack Module
- 16-bit AD977 A/D converter module
- 2 A/D modules each with 16 single-ended or 8 differential multiplexed A/D inputs for a total of 32 single-ended or 16 differential analog inputs
- Acquisition time of 100Ksps
- Programmable ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±3.3VDC, and 0-4VDC
- 64Kx18 FIFO enables burst mode or continuous sampling at lower throughput
- Channel 128K x 16 SRAM enables storage of gain, calibration, and input mode selection per input channel
- Differential inputs can be configured for single-ended, differential modes, or calibration modes (Vref or GND)
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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