IP-48-ADM

IP 16 bit A/D converter, 48 multiplexed input channels

  • 16-bit AD7671 A/D converter
  • Acquisition time of ≤2μsec (500Ksps)
  • Multiplexed 48 single-ended or 24 differential channels
  • Fault and over-voltage protected analog input (-40 VDC to +55 VDC)
  • Software programmable single-ended or differential input and gain for each channel
  • Input ranges: ±10VDC, ±5VDC, ±2.5VDC, ±1.25VDC via software programmable gain amplifier
  • A/D jumper selectable gain (1-2-4-8)
  • Internal sequencer with channel list for selected channel acquisition
  • On-board input switches for offset or gain calibration

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IP-48-ADM

IP 16 bit A/D converter, 48 multiplexed input channels

  • 16-bit AD7671 A/D converter
  • Acquisition time of ≤2μsec (500Ksps)
  • Multiplexed 48 single-ended or 24 differential channels
  • Fault and over-voltage protected analog input (-40 VDC to +55 VDC)
  • Software programmable single-ended or differential input and gain for each channel
  • Input ranges: ±10VDC, ±5VDC, ±2.5VDC, ±1.25VDC via software programmable gain amplifier
  • A/D jumper selectable gain (1-2-4-8)
  • Internal sequencer with channel list for selected channel acquisition
  • On-board input switches for offset or gain calibration

The IP-48-ADM multiplexed A/D module offers a versatile configuration with up to 48 single-ended or 24 differential analog input channels. Each channel is equipped with programmable gain and can be individually programmed to handle analog inputs in either single-ended or differential configurations, or in a calibration mode. The acquisition process can be initiated by the host or by an onboard sequencer that uses a channel list to specify which channels to acquire. The acquired data is stored in a local 64Kx16 dual-ported SRAM, allowing for efficient data handling. Memory pointers can be used to limit the number of scans gathered and control interrupt generation, providing flexible data management options.

Applications:

This is a perfect solution for:

  • Process control
  • Industrial control
  • Precision instrumentation
AD7671 A/D Device Specifications:
  • 16-bit, charge redistribution SAR, A/D converter
  • Hardware factory-calibrated and tested to ensure SNR and THD are within specifications
  • Gain, offset, and linearity are also factory-calibrated
  • Throughput
    1 MSPS (warp mode)
    800 kSPS (normal mode)
  • INL: ±2.5 LSB Max (±0.0038% of full scale) with no missing code
  • Analog input voltage ranges
    Bipolar: ±10 V, ±5 V, ±2.5 V
    Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
  • No pipeline delay
  • Single 5 V supply operation
Industry Pack Specifications:
  • Meets ANSI/VITA 4-1995
  • 8/32 MHz synchronous operation
  • Supports ID, 128 byte I/O, interrupt, & 8 Mbyte memory spaces
  • 2 Interrupts per module
  • Two passive DMA channels are possible
  • Hardware self timed per IP module
  • Triggered via system reset and software control
  • Jumper or software time-out function
  • 5, +/-12 volt reset-able fuse per IP
Mechanical: Environmental:
  • Size – VITA 4 compliant: 1.8″ x 3.9″ or 46 mm x 99 mm
  • Power – 1.0 watt
  • Vibration – 0.5G, 20-2000 Hz rand
  • Shock – 20G, 11 msec, 1⁄2 sine
  • Weight – 2 ounces
  • MTBF – >250,000 hours
Operating Environment:
  • Operating temperature
    Commercial: 0 to +70 °C
    Optional: -25 °C to +80 °C
  • Non-operating: -40 °C to +85 °C
  • Airflow requirement – 5 CFM
  • Humidity – 5 to 90% (non-cond)
  • Altitude – 0 to 10,000 feet

 

Part Numbers:

    • IP-48-ADM: 48 channel 16-bit A/D Industry Pack Module
    • IP-48-ADM-8: 8 channel 16-bit A/D Industry Pack Module
    • IP-48-ADM-8I: Same as above with -40 to +85°C operating temperature range

Optional Accessories:

  • Part Number: TB-50-HDR – 50 pin terminal block and 1 meter flat ribbon cable
  • Part Number: CBL-50-HDR – 50 pin, 1 meter flat ribbon cable, IDC header connector

Data Sheet – Link Here

User Manual – Link Here

  • 16-bit AD7671 A/D converter
  • Acquisition time of ≤2μsec (500Ksps)
  • Multiplexed 48 single-ended or 24 differential channels
  • Fault and over-voltage protected analog input (-40 VDC to +55 VDC)
  • Software programmable single-ended or differential input and gain for each channel
  • Input ranges: ±10VDC, ±5VDC, ±2.5VDC, ±1.25VDC via software programmable gain amplifier
  • A/D jumper selectable gain (1-2-4-8)
  • Internal sequencer with channel list for selected channel acquisition
  • On-board input switches for offset or gain calibration

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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