- Controller: Holt 3282 ARINC controller
- Channels: 1 transmitter and 2 receiver channels per controller, totaling 16 independent receive channels and 8 transmit channels
- Label Matching: Supports label matching for all receiver channels
- ARINC Compliance: Meets ARINC 429 specifications for loading, level detection, timing, and protocol
- Data Rate: Software-selectable data rate of 12.5kbps or 100kbps with automatic slew rate adjustment
- Operating Modes: Burst and continuous modes available
- Word Length and Parity: Programmable word length selection with automatic parity bit generation
- Buffer: 64kx16 SRAM buffer for data storage
- Clock Speeds: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
IP-ARINC-429
IP ARINC 429
- Controller: Holt 3282 ARINC controller
- Channels: 1 transmitter and 2 receiver channels per controller, totaling 16 independent receive channels and 8 transmit channels
- Label Matching: Supports label matching for all receiver channels
- ARINC Compliance: Meets ARINC 429 specifications for loading, level detection, timing, and protocol
- Data Rate: Software-selectable data rate of 12.5kbps or 100kbps with automatic slew rate adjustment
- Operating Modes: Burst and continuous modes available
- Word Length and Parity: Programmable word length selection with automatic parity bit generation
- Buffer: 64kx16 SRAM buffer for data storage
- Clock Speeds: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
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IP-ARINC-429
IP ARINC 429
The output board is designed for precise DC output control, utilizing FPGA controllers for accurate timing and functionality. Each output channel is optically isolated and features an open collector output. A PCI controller ensures seamless communication with the host computer, while all input/output connections are conveniently accessible on the front panel.
- FPGA Features
- Two independent 8-bit, double-buffered bidirectional I/O ports
- I/O ports feature programmable polarity
- Programmable direction at the bit level
- Flexible pattern-recognition logic; programmable as a 16-bit vector interrupt controller
- Three independent 16-bit counter/timers with up to four external access lines per counter/timer
- Four handshake modes
- All internal registers are readable and writable
- All registers have their own unique address so that they can be accessed directly
- PCI Bus Controller Features
- PLX 9056 33/66MHz 32-bit, PCI r2.2 compliant
- Motorola PowerQUICC and generic 32-bit, 66MHz local bus modes
- 3.3V I/O, 5V tolerant bus interfaces
- PICMG 2.1 r2.0 hot swap
- Zero wait state burst operation, with PCI bus bursts to 264 MB/sec and local bus bursts to 264 MB/sec
- 2 DMA channels
- Direct master data transfers
- Direct slave data transfers
- I/O Specifications
- 48 output pins, front panel accessible
- SCSI-style front panel connector
- Output supports continuous 100 mA DC load
- Optically isolated to 2500 VDC
- Output saturation of +0.3 VDC under 100 mA load
- Operating Environment
- Operating temperature: Commercial: 0 to +70 ºC, Optional: -40 ºC to +80 ºC
- Non-operating: -55 ºC to +95 ºC
- Airflow requirement – 5 CFM
- Humidity – 5 to 90% (non-cond)
- Altitude – 0 to 10,000 feet
- Mechanical Environment
- Size – 3U CPCI module, 100mm x 160mm
- Vibration – 0.5G, 20-2000 Hz random
- Shock – 20G, 11 msec, ½ sine
- Weight – 4 ounces
- MTBF – >250,000 hours
Ordering Information:
Part number: IP-ARINC-429 ARINC 429 controller on an Industry Pack module
Optional Accessories
Part number: TB-50-HDR 50 pin terminal block and 1 meter flat ribbon cable
CBL-50-HDR 50 pin, 1 meter flat ribbon cable, IDC header
connector
- Controller: Holt 3282 ARINC controller
- Channels: 1 transmitter and 2 receiver channels per controller, totaling 16 independent receive channels and 8 transmit channels
- Label Matching: Supports label matching for all receiver channels
- ARINC Compliance: Meets ARINC 429 specifications for loading, level detection, timing, and protocol
- Data Rate: Software-selectable data rate of 12.5kbps or 100kbps with automatic slew rate adjustment
- Operating Modes: Burst and continuous modes available
- Word Length and Parity: Programmable word length selection with automatic parity bit generation
- Buffer: 64kx16 SRAM buffer for data storage
- Clock Speeds: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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