All Features:

• Single-wide Industry Pack board
• Altera FPGA 10K50E, 10K100E, or 10K130E
• Up to 24 LVDS driver/receiver pairs (SN65MLVD204AD) or 48 TTL I/O lines
• Each line can be separately selected as input or output in TTL mode
• Programmable in groups of 4 I/O
• 100Ω terminating resistor or no resistor for LVDS I/O, resistor software selectable using MAX335 switch
• Up to 512K x 8 x 2 dual-ported SRAM
• EPM7160 timing device for IP bus, DPR bus, and FLEX device access
• 8 or 32 MHz clock
• Optional user clock on board running at different speed than IP bus
• 2 interrupts and 2 slave DMA IP bus lines
• FPGA programmable through bit/byte Blaster header, onboard serial EPROM, or through IP bus
• VITA 4 compliant

Available Software Drivers:

The customer must have an Altera development tool to implement their own FPGA design. The IP module can be used as a stand-alone module.

The FPGA’s program can be downloaded in one of three ways:

• • Bit/byte Blaster header connector connected directly to the FPGA
  • Local serial EPROM
  • Through the IP bus

Applications:

The IP-10K50E-PIO can be used as an LVDS bus I/O interface for parallel and/or serial communications between carrier systems or simply as a TTL I/O subsystem for monitoring and/or controlling digitally oriented functions.

The FPGA can be programmed through the Blaster interface for quick design turnaround. The local serial EPROM can be used for local programming. The FPGA can also be programmed by downloading the entire program into the FPGA from the IP bus for applications that require complete security.

SN65MLVD204AD LVDS Transceiver I/O Features (LVDS Mode):

• • • Signaling rates up to 100 Mbps, clock frequencies up to 50 MHz
    • Type 2 receivers provide an offset (100 mV) threshold to detect open-circuit and idle-bus conditions
    • Meets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint data interchange
    • Controlled driver output voltage transition times for improved signal quality
    • -1 V to 3.4 V common-mode voltage range allows data transfer with 2 V of ground noise
    • Differential output voltage magnitude = 650 mV max
    • Positive going differential input voltage threshold = 150 mV
    • Negative going differential input voltage threshold = 50 mV min
    • Differential input voltage hysteresis = 0 mV

FLEX I/O Features (TTL Mode):

• • • Low input voltage max = 0.8 VDC
    • High input voltage min = 2.0 VDC
    • Low output voltage max = 0.45 VDC
    • High output voltage min = 2.4 VDC
    • Max output current = 25 mA at Vcc = 5.0 VDC

Industry Pack Specifications:

• • • Meets ANSI/VITA 4-1995
    • 8/32 MHz synchronous operation
    • Supports ID, 128-byte I/O, interrupt, & 8 Mbyte memory spaces
    • 2 interrupts per module
    • Two passive DMA channels are possible
    • Hardware self-timed per IP module
    • Triggered via system reset and software control
    • Jumper or software time-out function
    • 5, +/-12 volt reset-able fuse per IP

Mechanical & Environmental:

• • • Size – VITA 4 compatible 1.8” x 3.9” (46 mm x 99 mm)
    • Power – 1.0 watt
    • Vibration – 0.5G, 20-2000 Hz random
    • Shock – 20G, 11 msec, ½ sine
    • Weight – TBD
    • MTBF – >250,000 hours

Operating Environment:

• • Operating temperature:
    • Commercial: 0 to +70 ºC
    • Optional: -25 ºC to +80 ºC
  • Non-operating: -40 ºC to +85 ºC
  • Airflow requirement – 5 CFM
  • Humidity – 5 to 90% (non-condensing)
  • Altitude – 0 to 10,000 feet