PCIe-XMC-IO

PCI Express to XMC Carrier with I/O Interface to Rear I/O

  • Full-size form factor (4.376in x 12.283in)
  • Single XMC carrier slot
  • XMC complies with ANSI/VITA42.0-2008
  • PCI Express x8 lanes
  • PCIe Specification, Rev 1.1
  • Gen 1 capable
  • Eight ports programmable for RS-422/RS-485
  • Configurable receiving port termination resistors

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PCIe-XMC-IO

PCI Express to XMC Carrier with I/O Interface to Rear I/O

  • Full-size form factor (4.376in x 12.283in)
  • Single XMC carrier slot
  • XMC complies with ANSI/VITA42.0-2008
  • PCI Express x8 lanes
  • PCIe Specification, Rev 1.1
  • Gen 1 capable
  • Eight ports programmable for RS-422/RS-485
  • Configurable receiving port termination resistors

The PCIe-XMC-IO is a PCI Express bus form factor XMC carrier. The carrier card interfaces an XMC mezzanine module to a PCI Express bus in a PC-based computer system. The PCIe bus adapter board allows a PC (PCIe bus master) to control and communicate with the hosted XMC module. It acts as an adapter to route signals between the system’s PCIe bus and the XMC module connector. The I/O signals for the XMC are routed to the rear I/O and used to provide additional ports controlled by the XMC module. A Stratum 3E DCOCXO High Stability 10MHz Oscillator provides a clock source for the XMC. The carrier board provides eight configurable RS-422/485 ports with termination, eight Open Collector output ports and eight LVTTL Input Ports with pull-ups. An extension cable is provided to connect the carrier’s rear I/O to a front panel connector in an adjacent slot.

All Technical Specifications

  • Full-size form factor (4.376in x 12.283in)
  • Single XMC carrier slot
  • XMC complies with ANSI/VITA42.0-2008
  • PCI Express x8 lanes
  • PCIe Specification, Rev 1.1
  • Gen 1 capable
  • Eight ports programmable for RS-422/RS-485
  • Configurable receiving port termination resistors
  • Eight OC (Open Collector) ports
  • Eight LVTTL inputs with pull-ups
  • Stratum 3E DCOCXO High Stability 10MHz Clock Oscillator
  • I/O available on 68-pin SCSI extension module
  • Custom carrier offered

Ordering Information

    • PCIe-XMC-IO
      • PCIe to XMC Slave Carrier with I/O and Bracket
    • PCIe-XMC-IO-NC
      • PCIe to XMC Slave Carrier with I/O and Bracket, No Clock

Optional Accessories

    • CBL-68-SCSI-Flat
      • 68 pin flat SCSI cable for Extender Connector – 10 inch
    • PCIe-EXT-68
      • 68 pin SCSI cable with PCI bracket mounted HD68 female connector – 10 inch

Data Sheet – Link Here

User Manual – Link Here

  • Full-size form factor (4.376in x 12.283in)
  • Single XMC carrier slot
  • XMC complies with ANSI/VITA42.0-2008
  • PCI Express x8 lanes
  • PCIe Specification, Rev 1.1
  • Gen 1 capable
  • Eight ports programmable for RS-422/RS-485
  • Configurable receiving port termination resistors

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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