PCI-1553-PLX-BCRTM

PCI MIL-STD-1553 BC/RT/MT Dual Redundant UTMC BCRTM Controller

  • UTMC BCRTM controller
  • 128Kbytes SRAM
  • On-chip Transceivers
  • On-board Transformers
  • Long stub / Short stub

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PCI-1553-PLX-BCRTM

PCI MIL-STD-1553 BC/RT/MT Dual Redundant UTMC BCRTM Controller

  • UTMC BCRTM controller
  • 128Kbytes SRAM
  • On-chip Transceivers
  • On-board Transformers
  • Long stub / Short stub

MIL-STD-1553 is a military standard defining a serial data bus used primarily in avionics and space applications. It features dual redundant channels (A and B) for high reliability and fault tolerance. The standard supports up to 31 remote terminals, with the 32nd typically reserved for broadcast messages. It operates at a data rate of 1 MHz, using Manchester II bi-phase encoding and a command/response protocol. The bus is half-duplex, meaning data can flow in both directions but not simultaneously. The specification includes options for operating temperatures ranging from 0 to +70 degrees Celsius and -25 to +80 degrees Celsius, with conformal coating available for environmental protection. The module includes 128 Kbyte SRAM and supports BC/RT/MT modes. It has separate logic for the PCI interface and supports both 3.3V and 5.0V I/O. The module uses 78 ohm transformers and supports long and short stub configurations. It is designed for low power consumption and includes LED status indicators. Available software includes C libraries, Windows, Linux, and VxWorks drivers. The module operates with a 33 MHz PMI clock and is PICMG compliant.

Memory

    • 128 Kbyte external SRAM

I/O

    • Dual 1553 bus levels
    • TTL (5v) clock

Programmable via

    • PCI Bus

PCI Interface

    • PLX 9080
    • 33 MHz clock
    • 5.0 & 3.3 VIO support
    • 16-bit address / data

Operating: Environmental

    • Operating temperature:
      • Commercial: 0 to +55 °C
      • Optional: -25°C to +80°C
    • Non-operating: -40°C to 85 °C
    • Airflow requirement: 0.5 CFM
    • Humidity: 5 to 90% (non-cond.)
    • Altitude: 0 to 10,000 ft

Mechanical: Environmental

    • Size: Half PCI
    • Power: 1.5 watt
    • Front panel I/O
    • Vibration: 0.5G RMS (20-2000 Hz random)
    • Shock: 20 G, 11 ms, ½ sine
    • Weight: TBD
    • MTBF: >150,000 hours

Ordering Information

    • Part Number: PCI-1553-PLX-bcrtm
      MIL-1553 BC/RT/M, PCI module
    • Part Number: PCI-1553-PLX-bcrtm-I
      same as above with -20 to +85 temperature rating

Optional Accessories

    • Part Number: EngKit-1553
      2 T’s, 2 Terminators, 2 1 meter cables
    • Part Number: CBL-1553-1
      Standard-standard 2 meter 1553 cable
    • Part Number: CBL-1553-2
      Standard-mini 2 meter 1553 cable
    • Part Number: CBL-1553-3
      Mini-mini 2 meter 1553 cable

Data Sheet – Link Here

User Manual – Link Here

  • UTMC BCRTM controller
  • 128Kbytes SRAM
  • On-chip Transceivers
  • On-board Transformers
  • Long stub / Short stub

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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