- Configuration: 4 A/D modules with 4 differential A/D inputs
- Acquisition Time: 1000Ksps
- Programmable Ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±2.5VDC, and 0-2.5VDC through A/D converter
- FIFO: 64Kx18 FIFO for burst mode or continuous sampling at lower throughput using control logic
- Trigger Modes: Pre-trigger and post-trigger acquisition
- Sampling Clock Sources: Internal divider (IPCLK/N), IPSTROBE, or External clock
- Trigger Event Sources: Write to IP register, IPSTROBE, or External trigger
- Clock Options: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- VITA Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
IP-AD-41M
IP 16 bit A/D converter, 4 A/D modules
- Configuration: 4 A/D modules with 4 differential A/D inputs
- Acquisition Time: 1000Ksps
- Programmable Ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±2.5VDC, and 0-2.5VDC through A/D converter
- FIFO: 64Kx18 FIFO for burst mode or continuous sampling at lower throughput using control logic
- Trigger Modes: Pre-trigger and post-trigger acquisition
- Sampling Clock Sources: Internal divider (IPCLK/N), IPSTROBE, or External clock
- Trigger Event Sources: Write to IP register, IPSTROBE, or External trigger
- Clock Options: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- VITA Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
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IP-AD-41M
IP 16 bit A/D converter, 4 A/D modules
The IP-AD-41-M has four 16-bit A/D converters that run simultaneously at 250Ksps with fault-protected front-end buffers. The A/D converters support unipolar and bipolar voltage inputs, including ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±2.5VDC, and 0-2.5VDC input ranges. They operate continuously at the selected sampling rate, with results stored in the FIFO or discarded as needed; only selected channels are saved into the FIFO, so the depth per channel is proportional to the number of channels saved. The IP module can be thought of as similar to a Digital Storage Oscilloscope (DSO), capable of storing and displaying several waveforms and recording signals prior to the trigger, with the trigger point configurable by reprogramming the FIFO’s programmable empty flag.
D/A Device Specifications
- 16-bit, monotonic D/A converter
- 16 output channels per D/A, 3 D/A’s total
- 20μsec settling time (50K conversions/sec) full-scale change
- Relative accuracy ±4 LSB max
- Zero scale error and full scale error 1 LSB typical after calibration
- Differential nonlinearity of ±1 LSB max
- Span error of offset D/A converter ±75mV max
- Slew rate 1 V/μsec typical
- Channel-to-channel isolation 100dB typical
- D/A-to-D/A crosstalk 10 nV-sec typical
- Nominal output range of -10VDC to +10VDC
- Load current ±1mA max
- Glitch impulse <20nV-sec
- D/A output amplified and buffered on-chip with respect to external SIGGNDx input
- D/A outputs can be switched to SIGGNDx
Driver Output Specifications
- Inherent short-circuit protection to ground of 40mA
- Low offset voltage 250uV laser-trimmed
- High slew rate 22V/usec
- Low offset current 2nA
- Low distortion 0.0006%
- Wide bandwidth 9MHz
Industry Pack Specifications
- Meets ANSI/VITA 4-1995
- 8/32 MHz synchronous operation
- Supports ID, 128 byte I/O, interrupt, & 8 Mbyte memory spaces
- 2 Interrupts per module
- Two passive DMA channels are possible
- Hardware self timed per IP module
- Triggered via system reset and software control
- Jumper or software time-out function
- 5, +/-12 volt reset-able fuse per IP
Mechanical: Environmental
- Size – VITA 4 compliant: 1.8″ x 3.9″ or 46 mm x 99 mm
- Power – 1.0 watt
- Vibration – 0.5G, 20-2000 Hz rand
- Shock – 20G, 11 msec, 1⁄2 sine
- Weight – tbd
- MTBF – >250,000 hours
Operating Environment
- Operating temperature
- Commercial: 0 to +70°C
- Optional: -25°C to +80°C
- Non-operating: -40°C to +85°C
- Airflow requirement – 5 CFM
- Humidity – 5 to 90% (non-condensing)
- Altitude – 0 to 10,000 feet
Part number: IP-AD-41M 4 channel, 16 bit, 1000ksps A/D Industry Pack Module
- Configuration: 4 A/D modules with 4 differential A/D inputs
- Acquisition Time: 1000Ksps
- Programmable Ranges: ±10VDC, 0-10VDC, ±5VDC, 0-5VDC, ±2.5VDC, and 0-2.5VDC through A/D converter
- FIFO: 64Kx18 FIFO for burst mode or continuous sampling at lower throughput using control logic
- Trigger Modes: Pre-trigger and post-trigger acquisition
- Sampling Clock Sources: Internal divider (IPCLK/N), IPSTROBE, or External clock
- Trigger Event Sources: Write to IP register, IPSTROBE, or External trigger
- Clock Options: 8 or 32 MHz clock
- Interrupts and DMA: 2 interrupts and 2 slave DMA IP bus lines
- VITA Compliance: VITA 4 compliant
- EEPROM: 32 bytes used for board ID
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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