IP-48AD

IP 16 bit A/D converter, 8 A/D modules, 48 input channels

  • 16-bit AD7656 A/D converter module
  • 8 A/D modules each with 6 independent A/D channels for a total of 48 single-ended A/D’s
  • Acquisition time of 250Ksps
  • Input ranges: ±10VDC, ±5VDC (software selectable or pin selectable)
  • 64Kx16 FIFO enables burst mode or continuous sampling
  • Sampling clock selected from one of the following sources:
    • Internal divider (TCLK0)
    • IPSTROBE
    • External clock
    • Host

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IP-48AD

IP 16 bit A/D converter, 8 A/D modules, 48 input channels

  • 16-bit AD7656 A/D converter module
  • 8 A/D modules each with 6 independent A/D channels for a total of 48 single-ended A/D’s
  • Acquisition time of 250Ksps
  • Input ranges: ±10VDC, ±5VDC (software selectable or pin selectable)
  • 64Kx16 FIFO enables burst mode or continuous sampling
  • Sampling clock selected from one of the following sources:
    • Internal divider (TCLK0)
    • IPSTROBE
    • External clock
    • Host

The IP-48AD-16 module contains 48 simultaneous channels of A/D conversion using a 16-bit, fast, successive approximation A/D’s. The module can accept bipolar input signals at rates up to 250ksps, and the analog input signals are buffered with a fast buffer amplifier. The A/D contains low noise, wide bandwidth track-and-hold amplifiers that can handle input frequencies up to 8MHz.

The acquisition can be started by the host, a write to the IP register, activation of the IPSTROBE signal, or an external trigger. A state machine will read the data of each individually selected A/D channel into the FIFO.

FIFO pointers are used to monitor, stop or “throttle” the acquisition and inform the user by means of status or interrupt the progress of the acquired data.

The A/D converter data can be read directly by the host if desired bypassing the FIFO. The sampling clock is available from an internal divider and the TCLK0 input, IPSTROBE signal, an external clock, or the host. Sampling occurs with A/D pairs.

The board ID can be read from the on-board EEPROM.

Applications:

  • Process control
  • Power line monitoring
  • Multi-axis positioning systems
  • Industrial control
  • Precision instrumentation

AD7656 A/D Specifications:

  • 16-bit, successive approximation A/D’s
  • 6 independent A/D’s
  • Fast throughput rate of 250ksps
  • Wide input bandwidth of 86.5 dB SNR at 50kHz input frequency
  • Can accept true bipolar inputs up to ±4VDC x Vref
  • External pins allow independent, simultaneous sampling of 3 A/D pairs
  • Analog input voltage ranges: ±10 V, ±5 V
  • Contains on-chip 2.5VDC reference
  • Single 5 V supply operation

Input Buffer LT1468 Specifications:

  • 900MHz gain bandwidth, f= 100kHz
  • 22V/μsec slew rate
  • Settling time 900 nsec
  • Low distortion -96.5 db for 100kHz, 10Vp-p
  • Unity gain stable

Industry Pack Specifications:

  • Meets ANSI/VITA 4-1995
  • 8/32 MHz synchronous operation
  • Supports ID, 128 byte I/O, interrupt, & 8 Mbyte memory spaces
  • 2 Interrupts per module
  • Two passive DMA channels are possible
  • Hardware self-timed per IP module
  • Triggered via system reset and software control
  • Jumper or software time-out function
  • 5, +/-12 volt reset-able fuse per IP

Mechanical: Environmental:

  • Size – VITA 4 compliant (1.8” x 3.9” or 46 mm x 99 mm)
  • Power – 1.0 watt
  • Vibration – 0.5G, 20-2000 Hz rand
  • Shock – 20G, 11 msec, ½ sine
  • Weight – 1 ounce
  • MTBF – >250,000 hours

Operating Environment:

  • Operating temperature: Commercial (0 to +70 ºC), Optional (-40 ºC to +85 ºC)
  • Non-operating: -45 ºC to +90 ºC
  • Airflow requirement – 5 CFM
  • Humidity – 5 to 90% (non-cond)
  • Altitude – 0 to 10,000 feet

Ordering Information:

  • Part Number: IP-48AD-16
    48 channel 16-bit A/D Industry Pack Module
  • Part Number: IP-48AD-16 – I
    Same as above with -40°C to +85°C operating temperature range

Optional Accessories:

  • Part Number: TB-50-HDR
    50 pin terminal block and 1 meter flat ribbon cable
     
  • Part Number: CBL-50-HDR
    50 pin, 1 meter flat ribbon cable, IDC header connector

Data Sheet – Link Here

User Manual – Link Here

  • 16-bit AD7656 A/D converter module
  • 8 A/D modules each with 6 independent A/D channels for a total of 48 single-ended A/D’s
  • Acquisition time of 250Ksps
  • Input ranges: ±10VDC, ±5VDC (software selectable or pin selectable)
  • 64Kx16 FIFO enables burst mode or continuous sampling
  • Sampling clock selected from one of the following sources:
    • Internal divider (TCLK0)
    • IPSTROBE
    • External clock
    • Host

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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