PSCC – 1028

OCTAL RS-232 & RS-485/422 UART

  • 8-channel UART
  • RS-232 and RS-422/485 software programmable interfaces
  • IEEE 1386.1-2001 PMC module
  • 32-bit @ 33MHz PCI interface
  • 3.3 V and 5 V PCI signaling
  • Up to 6.25 Mbps data rate @ RS-422/485
  • Up to 250 kbps data rate @ RS-232
  • Half and full duplex modes support
  • Conduction cooling compatible
  • Industrial temperature range -40/+85 °C

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PSCC – 1028

OCTAL RS-232 & RS-485/422 UART

  • 8-channel UART
  • RS-232 and RS-422/485 software programmable interfaces
  • IEEE 1386.1-2001 PMC module
  • 32-bit @ 33MHz PCI interface
  • 3.3 V and 5 V PCI signaling
  • Up to 6.25 Mbps data rate @ RS-422/485
  • Up to 250 kbps data rate @ RS-232
  • Half and full duplex modes support
  • Conduction cooling compatible
  • Industrial temperature range -40/+85 °C
The PSCC-1028 is an octal asynchronous serial communication controller in PMC form factor, compatible with PCI specification 2.3 and supporting 32-bit bus at 33 MHz with both 3.3V and 5V signaling24. It features 8 enhanced 16550 UARTs, each with 64-byte transmit and receive FIFOs, individual baud rate generators, and software-programmable RS-232 and RS-422/485 interfaces supporting up to 250 kbps and 6.25 Mbps data rates respectively24. The module offers front panel SCSI-3 68-pin and rear I/O P4 connectors, with alternative versions available including isolated variants. It supports major real-time operating systems, Linux, and VxWorks, making it versatile for various applications requiring high-speed serial communication.
Octal UART
  • 16C550 compatible 5G register set UART
  • Integrated receive and transmit FIFO+central FIFO
Line interface
  • RS-232 and RS-422/485 software programmable interface
  • Up to 6.25 Mbps data rate (RS422/485)
  • Up to 250 kbps data rate (RS232)
  • Up to 256 RS-485 transmitters bus topology
  • Full and half duplex modes support
PCI Interface
  • 32-bit/33 MHz interface
  • PCI revision 2.3 compliant
  • 3.3 V and 5 V environment support
I/O connection
  • Serial communication I/Os available on SCSI-3 68-pin front panel connector and P4 mezzanine rear I/O connector
  • On-board RS-422/RS-485 network terminations
Environmental
  • Operating: -40 to 85 °C
  • Storage: -65 to 125 °C
  • Airflow requirement: 0 CFM
  • Relative Humidity: 0 to 90 % (non-cond.)
  • Altitude: 0 to 3000 m (10,000 ft)
Mechanical
  • Dimensions: 149 x 74 mm
  • Power: TBD
  • Vibration: 0.5 G/Hz, 0-2000 Hz random
  • Shock: 20 G, 11 ms, ½ sine

For ordering information, please visit our web site at www.actis-computer.com

Data Sheet – Link Here

  • 8-channel UART
  • RS-232 and RS-422/485 software programmable interfaces
  • IEEE 1386.1-2001 PMC module
  • 32-bit @ 33MHz PCI interface
  • 3.3 V and 5 V PCI signaling
  • Up to 6.25 Mbps data rate @ RS-422/485
  • Up to 250 kbps data rate @ RS-232
  • Half and full duplex modes support
  • Conduction cooling compatible
  • Industrial temperature range -40/+85 °C

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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