PCIe-6713-ISC8

PCIe 320C6317B DSP Octal Serial Controller

  • DSP: Based on the Texas Instruments floating-point Digital Signal Processor TMS320C6713B at 300 MHz
  • Serial Controllers: Quad 16 MHz SCC85230 serial controllers with 8 serial channels total
  • I/O Options: Optional mezzanine-based I/O or RS232C/RS422/RS485 drivers
  • PCI Express Interface: PCIe x1 lane, compliant with PCIe Specification r1.0a, offering up to 250 MB/s bandwidth39
  • Front Panel I/O: Front panel serial I/O available
  • Communication Protocols: Multi-protocol support including synchronous, asynchronous, Bisync, Xon/Xoff, HDLC, or SDLC communication protocols
  • Performance: Adds high-speed, low latency I/O and deterministic control to a low-cost PC system solution

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PCIe-6713-ISC8

PCIe 320C6317B DSP Octal Serial Controller

  • DSP: Based on the Texas Instruments floating-point Digital Signal Processor TMS320C6713B at 300 MHz
  • Serial Controllers: Quad 16 MHz SCC85230 serial controllers with 8 serial channels total
  • I/O Options: Optional mezzanine-based I/O or RS232C/RS422/RS485 drivers
  • PCI Express Interface: PCIe x1 lane, compliant with PCIe Specification r1.0a, offering up to 250 MB/s bandwidth39
  • Front Panel I/O: Front panel serial I/O available
  • Communication Protocols: Multi-protocol support including synchronous, asynchronous, Bisync, Xon/Xoff, HDLC, or SDLC communication protocols
  • Performance: Adds high-speed, low latency I/O and deterministic control to a low-cost PC system solution

The board features private SDRAM and Flash memory attached to a DSP, with an FPGA providing timing and control. Peripherals include a serial port and connectors for IP mezzanine boards, allowing for flexible expansion and integration of additional functionalities. The Flash memory is utilized for downloading programs into non-volatile memory, ensuring persistent storage of configurations and applications. A PCIe 1x lane bus connector serves as the interface to the host computer, facilitating communication and data transfer between the board and the host system. The PCIe-6713-ISC8 module is ideal for applications requiring low-cost, high-density I/O or unique combinations. It can be used to simply move data to and from the PCIe bus or to provide multi-protocol support up to the application level. Custom application software can be downloaded to the DSP via the PCIe bus, allowing for flexible and customizable solutions.

DSP Features

  • TMS320C6713B DSP @ 300 MHz
  • 32/64-bit data word
  • Executes up to 8 32-bit instructions per cycle
  • Up to 2400 MIPS/MFLOPS
  • Advanced VLIW DSP core with 8 independent functional units:
    • 2 fixed-point ALUs
    • 4 floating/fixed-point ALUs
    • 2 floating/fixed-point multipliers
  • L1/L2 memory architecture:
    • 4K-byte L1P program cache
    • 4K-byte L1D data cache (2-way)
    • 256K-byte L2 memory with 64K-byte unified cache/mapped RAM and 192K-byte additional mapped RAM
  • Load-store architecture with 32 32-bit general-purpose registers
  • Native instructions for IEEE 754 single and double precision operations
  • 32-bit external memory interface with glueless interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
  • 512 Mbyte total addressable external memory space
  • Dual 32-bit general-purpose timers
  • 16-channel Enhanced DMA (EDMA)
  • Two Inter-Integrated Circuit (I2C) buses
  • 16-bit Host-Port Interface (HPI)
  • IEEE-1149.1 (JTAG) boundary scan compatible

85230 Features

  • 16 MHz clock
  • Programmable synchronous and isosynchronous data rates
  • Asynchronous capabilities
  • 5, 6, 7, or 8 bits per character
  • 1, 1.5, or 2 stop bits
  • Odd or even parity
  • 1x, 16x, 32x, or 64x clock modes
  • Direct byte-oriented synchronous support
  • Direct SDLC/HDLC support
  • Receiver/transmitter FIFO
  • DPLL for clock recovery
  • Baud rate generator for each channel
  • NRZ, NRZI, or FM encoding/decoding with Manchester coding support

PCIe Bus Features

  • 3.3V I/O, 5V tolerant bus interfaces
  • Local Bus Clock rates at 66MHz
  • Compliant with PCIe Specification, r1.0a
  • PCIMG 1.x compliant
  • Multiple DMA operational modes
  • Direct master data transfers
  • Direct slave data transfers
  • Power consumption: 1.0 Watt

Operating Environment

  • Operating temperature:
    • Commercial: 0 to +70 °C
    • Optional: -25 °C to +80 °C
  • Non-operating temperature: -40 °C to +85 °C
  • Airflow requirement: 5 CFM
  • Humidity: 5 to 90% (non-condensing)
  • Altitude: Up to 10,000 feet

Mechanical Environment

  • Size: Standard Full-size PCI Express Card
  • Power consumption: 1.0 watt
  • Vibration resistance: 0.5G, 20-2000 Hz random
  • Shock resistance: 20G, 11 ms, ½ sine
  • Weight: To be determined
  • MTBF: >250,000 hours

Software Drivers

  • Linux drivers
  • Windows XP drivers
  • VxWorks drivers
  • C library DLLs

Software Tools

  • TI eXpressDSP development tools
  • Code Composer Studio (CCS) Integrated Development Environment (IDE)
  • JTAG-based emulation for real-time debugging
  • DSP/BIOS kernel for real-time operating system support

Part Number: PCIe-6713B-ISC8-1

    • 3U 320C6713B DSP with 8 serial communication channels
  • Part Number: PCIe-6713B-ISC8-2
    • 3U 320C6713B DSP with WANTap
  • Part Number: PCIe-6713B-ISC8-3
    • 3U 320C6713B DSP – 8 x RS 422
  • Part Number: PCIe-6713B-ISC8-4
    • 3U 320C6713B DSP – 8 x RS 232

Optional Accessories:

  • Part Number: CBL-50-HRS
    • Cable
  • Part Number: TB-50-HRS
    • Terminal block

Data Sheet – Link Here

User Manual – Link Here

  • DSP: Based on the Texas Instruments floating-point Digital Signal Processor TMS320C6713B at 300 MHz
  • Serial Controllers: Quad 16 MHz SCC85230 serial controllers with 8 serial channels total
  • I/O Options: Optional mezzanine-based I/O or RS232C/RS422/RS485 drivers
  • PCI Express Interface: PCIe x1 lane, compliant with PCIe Specification r1.0a, offering up to 250 MB/s bandwidth39
  • Front Panel I/O: Front panel serial I/O available
  • Communication Protocols: Multi-protocol support including synchronous, asynchronous, Bisync, Xon/Xoff, HDLC, or SDLC communication protocols
  • Performance: Adds high-speed, low latency I/O and deterministic control to a low-cost PC system solution

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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