| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) |
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) |
| PCI Express Switch | PI7C9X2G312GP (Pericom) |
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) |
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) |
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage |
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit |
| Board Configuration Controller | LCMXO2-7000HC (Lattice) |
| ADC | LTC2320 -16 (Analog Devices) |
| DAC | AD5547BRUZ (Analog Devices) |
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz |
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs |
| Digital Front I/O Channels | 32 digital I/O Lines - Default configured as 32 ESD-protected TTL lines
- 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
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| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector - Can be used as single-ended or differential I/O
- FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25
4 MGT line to P16 Rear I/O connector - Each line consists of one differential RX and TX pair.
- Transmission speeds of up to 3.125 Gb/s are possible.
|
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR |
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) |
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) |
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load | | typical @ +12 V VPWR | typical @ +5 V VPWR | | TXMC639-10R | 1.1 A | 2.5 A | | TXMC639-11R | 1.3 A | 3.3 A |
|
| Temperature Range | Operating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C |
| MTBF 1) | 157 000 h to 161 000 h |
| Humidity | 5% – 95% non-condensing |
| Weight | 140 g |
