- AXM interface board
- 64 I/O Channels
- Switch between 3.3-V LVTTL and 5V JEDEC standards (JESD8C.01)
- Translate the two standards into an LVCMOS JEDEC standard for the FPGA pin connections
- 64 I/O can be programmed to have resistors that pull the IO pins to the programmed VCC, or ground in banks of 8
- Power-up Controller to allow Pull-up or Pull-down
- Front Panel MDR Connector
AXM-DIO64
AXM FGA INTERFACE 64 Digital I/O Controller
- AXM interface board
- 64 I/O Channels
- Switch between 3.3-V LVTTL and 5V JEDEC standards (JESD8C.01)
- Translate the two standards into an LVCMOS JEDEC standard for the FPGA pin connections
- 64 I/O can be programmed to have resistors that pull the IO pins to the programmed VCC, or ground in banks of 8
- Power-up Controller to allow Pull-up or Pull-down
- Front Panel MDR Connector
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AXM-DIO64
AXM FGA INTERFACE 64 Digital I/O Controller
The Alphi Technology AXM-DIO64 module enhances programmable logic boards with raw FPGA connections through a standard AXM connector. It is designed to switch seamlessly between 3.3V LVTTL and 5V JEDEC standards (JESD8C.01), translating these external I/O standards into the LVCMOS JEDEC standard for FPGA pin connections. The module also supports configurable pull-up or pull-down resistors in banks of 8, allowing the I/O pins to be programmed to the desired VCC or ground. The AXM-DIO64 provides a flexible and robust solution for interfacing FPGAs with various external devices and systems, offering versatility in digital I/O applications.
Ordering Information
- AXM-DIO64
AXM 64 Digital I/O channels
Option (add following the part number)
- C (Conformal coat)
Optional Accessories
- CBL-MDR-68 68 Pins MDR Cable 1M
- AXM interface board
- 64 I/O Channels
- Switch between 3.3-V LVTTL and 5V JEDEC standards (JESD8C.01)
- Translate the two standards into an LVCMOS JEDEC standard for the FPGA pin connections
- 64 I/O can be programmed to have resistors that pull the IO pins to the programmed VCC, or ground in banks of 8
- Power-up Controller to allow Pull-up or Pull-down
- Front Panel MDR Connector
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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