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	<title>FPGA &#8211; ALPHI Technology</title>
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	<title>FPGA &#8211; ALPHI Technology</title>
	<link>https://www.alphitech.com</link>
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		<title>QMC-XCAU7P</title>
		<link>https://www.alphitech.com/products/qmc/qmc-xcau7p/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Tue, 11 Nov 2025 00:42:22 +0000</pubDate>
				<guid isPermaLink="false">https://www.alphitech.com/?post_type=product&#038;p=7132</guid>

					<description><![CDATA[QMC PCIe x4 User Reconfigurable AMD-XILINX ARTIX ULTRASCALE+ FPGA 20 Channels RS-422/485 OR 40 Channels LVTTL]]></description>
										<content:encoded><![CDATA[<ul>
<li>QMC PCI Express x4 lane interface</li>
<li>QMC 26mm x 78.25 mm</li>
<li>User-reconfigurable AMD-Xilinx Artix UltraScale+ FPGA</li>
<li>Up to 20 Pairs RS-422/485 bidirectional channels, 20Mb/s data rate per channel, software-selectable half or full duplex, or Up to 40 Channels LVTTL</li>
<li>Software-selectable 120Ω termination</li>
<li>Software-programmable interrupts for Change-of-State/Level detection</li>
<li>High Precision User Clock PPB Input on Board</li>
<li>Optional ARINC-429 Receiver</li>
</ul>
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		<item>
		<title>M.2-XCAU7P-FPGA</title>
		<link>https://www.alphitech.com/products/m-dot-2/m-2-xcau7p-fpga/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 10 Feb 2025 09:55:58 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4323</guid>

					<description><![CDATA[M.2 PCIe x4 USER RECONFIGURABLE AMD-XILINX ARTIX ULTRASCALE+ FPGA 16 Channels RS-422/485 OR 32 Channels LVTTL]]></description>
										<content:encoded><![CDATA[<ul>
<li>M.2 PCI Express x4 lane interface</li>
<li>M.2 2260 support Key M &amp; B</li>
<li>User-reconfigurable AMD-Xilinx Artix UltraScale+ FPGA</li>
<li>Up to 16 Pairs RS-422/485 bidirectional channels, 20Mb/s data rate per channel, software-selectable half or full duplex, or up to 32 Channels LVTTL</li>
<li>Software-selectable 120Ω termination</li>
<li>Software-programmable interrupts for Change-of-State/Level detection</li>
<li>High Precision User Clock PPB Input on Board</li>
</ul>
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			</item>
		<item>
		<title>IP-CYCLONE-IV-PIO</title>
		<link>https://www.alphitech.com/products/ip/ip-cyclone-iv-pio/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 10 Feb 2025 08:20:11 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4277</guid>

					<description><![CDATA[USER RECONFIGURABLE ALTERA CYCLONE IV 64MBYTES DUAL-PORTED DDR RS-422/485, TTL OR COMBINATION I/O DRIVERS]]></description>
										<content:encoded><![CDATA[<ul>
<li>Altera Cyclone IV FPGA EP4CE30, 55, 75, 115</li>
<li>Stand alone possibility</li>
<li>Single wide Industry Pack</li>
<li>20 Mbps RS485</li>
<li>Logic-Selectable 120Ω Termination Resistor</li>
<li>Optional User clock oscillator</li>
</ul>
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		<title>IP-10K50E-PIO</title>
		<link>https://www.alphitech.com/products/ip/ip-10k50e-pio/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Sun, 09 Feb 2025 10:02:55 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4234</guid>

					<description><![CDATA[IP ALTERA 10K50E with RS485/RS422/TTL Parallel I/O]]></description>
										<content:encoded><![CDATA[<ul class="marker:text-textOff list-disc pl-8">
<li><span class="">Single-wide Industry Pack board</span></li>
<li><span class="">Altera FPGA 10K50E, 10K100E, or 10K130E</span></li>
<li><span class="">Up to 24 RS485 or RS422 driver/receiver (MAX1484) or TTL input/output lines</span></li>
<li><span class="">Each line can be separately selected as input or output</span></li>
<li><span class="">Programmable in groups of 4 I/O</span></li>
<li><span class="">100Ω terminating resistor or no resistor for RS485/RS422 I/O, resistor software selectable using MAX335 switch</span></li>
<li><span class="">Up to 512K x 8 x 2 dual-ported SRAM</span></li>
<li><span class="">EPM7160 timing device for IP bus, DPR bus, and FLEX device access</span></li>
</ul>
]]></content:encoded>
					
		
		
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		<title>IP-10K50E-LVDS</title>
		<link>https://www.alphitech.com/products/ip/ip-10k50e-lvds/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Sun, 09 Feb 2025 09:56:37 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4232</guid>

					<description><![CDATA[IP ALTERA 10K50E with LVDS Parallel I/O]]></description>
										<content:encoded><![CDATA[<ul class="marker:text-textOff list-disc pl-8">
<li><span class="">Single-wide Industry Pack board</span></li>
<li><span class="">Altera FPGA 10K50E, 10K100E, or 10K130E</span></li>
<li><span class="">Up to 24 LVDS driver/receiver pairs (SN65MLVD204AD) or 48 TTL I/O lines</span></li>
<li><span class="">Each line can be separately selected as input or output in TTL mode</span></li>
<li><span class="">Programmable in groups of 4 I/O</span></li>
<li><span class="">100Ω terminating resistor or no resistor for LVDS I/O, resistor software selectable using MAX335 switch</span></li>
<li><span class="">Up to 512K x 8 x 2 dual-ported SRAM</span></li>
<li><span class="">EPM7160 timing device for IP bus, DPR bus, and FLEX device access</span></li>
</ul>
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