- 3U PXIe form factor
- Single XMC carrier slot
- XMC Complies with ANSI/VITA 42.0-2008
- PXI Express x8 Lanes
- X8 Lanes support up to 8Gbps
- PCIeGen-1,2,and3 Capable
- Connect User I/O from XMC to Clock and Trigger lane on XJ4
- On board XMC JTAG connector
- FPGA I/O bank control to PXI interface including Trigger and Clock
PXIe-XMC-IO
PXIexpress to XMC Non Intelligent Carrier with I/O Interface to Rear I/O
- 3U PXIe form factor
- Single XMC carrier slot
- XMC Complies with ANSI/VITA 42.0-2008
- PXI Express x8 Lanes
- X8 Lanes support up to 8Gbps
- PCIeGen-1,2,and3 Capable
- Connect User I/O from XMC to Clock and Trigger lane on XJ4
- On board XMC JTAG connector
- FPGA I/O bank control to PXI interface including Trigger and Clock
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PXIe-XMC-IO
PXIexpress to XMC Non Intelligent Carrier with I/O Interface to Rear I/O
The PXIe-XMC-IO carrier allows a standard XMC module to be used in a PXI Express slot.
The carrier card interfaces an XMC mezzanine module to a PXI Express bus with up to 8 Gbps support in a PXIe Chassis computer system. The PXIe bus adapter board allows a PXIe (PXIe bus master) to control and communicate with the hosted XMC module. It acts as an adapter to route signals between the system’s PXIe bus and the XMC module connector. The I/O signals from the XMC are routed to the rear I/O and used to provide additional Ports controlled by the XMC. The added I/O ports are electrically controlled by the XMC module. The PXIe and PXI signals are routed to the FPGA via the user I/O J14 on the XMC.
Ordering Information
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- PXIe-XMC-IO PXIe to XMC Carrier with I/O
- PXIe-XMC-IO-2 PXIe to XMC Carrier with I/O, No J14
- 3U PXIe form factor
- Single XMC carrier slot
- XMC Complies with ANSI/VITA 42.0-2008
- PXI Express x8 Lanes
- X8 Lanes support up to 8Gbps
- PCIeGen-1,2,and3 Capable
- Connect User I/O from XMC to Clock and Trigger lane on XJ4
- On board XMC JTAG connector
- FPGA I/O bank control to PXI interface including Trigger and Clock
| Mechanical Interface | Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard) Standard single-width (149mm x 74mm) | |||||||||
| Electrical Interface | PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard) | |||||||||
| PCI Express Switch | PI7C9X2G312GP (Pericom) | |||||||||
| PCI Express to PCI Bridge | XIO2001 (Texas Instruments) | |||||||||
| User configurable FPGA | TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) | |||||||||
| SPI-Flash | MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage | |||||||||
| DDR3 RAM | 2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit | |||||||||
| Board Configuration Controller | LCMXO2-7000HC (Lattice) | |||||||||
| ADC | LTC2320 -16 (Analog Devices) | |||||||||
| DAC | AD5547BRUZ (Analog Devices) | |||||||||
| A/D Channels | TXMC639-10R: 8 Differential 16bit A/D Channels TXMC639-11R: 16 Differential 16bit A/D Channels Input Configuration per BCC Device: Input Voltage Ranges: Differental : ±20.57 V, ±10.28 V or ±5.14 V (Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V) All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs. The -3 dB limit of this input stage is at approx. 8MHz | |||||||||
| D/A Channels | TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels Output range configurable per D/A channel. Maximum single-ended Output Voltage – Vout: ±10 V Maximum Output Drive Current for each Output: 10 mA Maximum Capacitive Load for each Output: 1000 pF Typical Settling Time for a 10 mA / 1000 pF: < 1 µs | |||||||||
| Digital Front I/O Channels | 32 digital I/O Lines
| |||||||||
| Digital Rear I/O Channels | 64 direct FPGA I/O lines to P14 Rear I/O connector
4 MGT line to P16 Rear I/O connector
| |||||||||
| Front I/O | Front I/O Samtec – ERF8_050_01_L_D_RA_L_TR | |||||||||
| P14 Rear I/O | 64 pin Mezzanine Connector (Molex 71436-2864 or compatible) | |||||||||
| P16 Rear I/O | 114 pin Mezzanine Connector (Samtec – ASP-105885-01) | |||||||||
| Power Requirements 1) | Depends on FPGA design With TXMC639 Board Reference Design / without external load
| |||||||||
| Temperature Range | Operating: – 40 °C to + 85 °C Storage: – 55 °C to + 125 °C | |||||||||
| MTBF 1) | 157 000 h to 161 000 h | |||||||||
| Humidity | 5% – 95% non-condensing | |||||||||
| Weight | 140 g |
1) depends on variant, for further details see User Manual
TXMC639-10R
| 8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
TXMC639-11R
| 16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O |
SOFTWARE
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