PXIe-SCC08F

PXIe Octal Serial I/O With 4K FIFO

  • Eight Z85233 Enhanced Controller
  • Octal synchronous / Asynchronous serial ports
  • 4K FIFO per Line (TX and RX)
  • Software selectable RS-232 or RS-422, RS-485 HDLC, SDLC
  • Individual baud rate generators per port
  • 230 Kbits Async, up to 2 Mbits Sync
  • Full handshake control line
  • Software programmable 120 Ohm Termination
  • Full modem control
  • Software examples included

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PXIe-SCC08F

PXIe Octal Serial I/O With 4K FIFO

  • Eight Z85233 Enhanced Controller
  • Octal synchronous / Asynchronous serial ports
  • 4K FIFO per Line (TX and RX)
  • Software selectable RS-232 or RS-422, RS-485 HDLC, SDLC
  • Individual baud rate generators per port
  • 230 Kbits Async, up to 2 Mbits Sync
  • Full handshake control line
  • Software programmable 120 Ohm Termination
  • Full modem control
  • Software examples included

The PXIe-SCC08F module is an Octal channel serial communication controller with 4K Fifo per Line. The PXIe-SCC08F module is based on 8 enhanced Z85233, with larger FIFOs and several SDLC improvements from Zilog. This module provides Eight asynchronous ports up to 230 kbaud and synchronous ports up to 2 Mbaud full-duplex channels, with an independent baud rate generator for each channel. Several types of interface are supported by the PXIe-SCC08F module: – RS-232 and RS-422 / RS-485 with programmable 120 Ohm Termination User Clock for Baud rate generator.

PXIe Interface

    • Compatible with PXIe Bus specification
    • X1 PCIexpress Lane
    • Local Bus Clock rates at 66MHz
    • Multiple DMA operational modes
    • Direct master data transfers
    • Direct slave data transfers

Operating: Environmental

    • Operating temperature:
      • Commercial: 0 to +70 °C
      • Optional: -25°C to +80°C
    • Non-operating: -40°C to 85°C
    • Airflow requirement: 0.5 CFM
    • Humidity: 5 to 90% (noncondensing)
    • Altitude: 0 to 10,000 ft

Mechanical: Environmental

    • Size: Vita 4 Type 1 IP (1.8” x 3.9”)
    • Power: +5, +12, -12 volts
    • Vibration: 0.5G RMS (20-2000 Hz rand)
    • Shock: 20 G, 11 ms, ½ sine
    • Weight: TBD
    • MTBF: >250,000 hours

Ordering Information

    • Part Number: PXIe-SCC08F
      8 Ch RS-422/RS-485 Module

Optional Accessories

    • Part Number: TB-68-MDR
      68 pin terminal block and 1meter flat ribbon cable
    • Part Number: CBL-68-MDR
      68 pin, MDR Cable connector

Data Sheet – Link Here

  • Eight Z85233 Enhanced Controller
  • Octal synchronous / Asynchronous serial ports
  • 4K FIFO per Line (TX and RX)
  • Software selectable RS-232 or RS-422, RS-485 HDLC, SDLC
  • Individual baud rate generators per port
  • 230 Kbits Async, up to 2 Mbits Sync
  • Full handshake control line
  • Software programmable 120 Ohm Termination
  • Full modem control
  • Software examples included

 

Mechanical Interface

Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical InterfacePCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express SwitchPI7C9X2G312GP (Pericom)
PCI Express to PCI BridgeXIO2001 (Texas Instruments)
User configurable FPGA

TXMC639-10R: XC7K160T-2FBG676I (AMD)

TXMC639-11R: XC7K325T-2FBG676I (AMD)

SPI-FlashMT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage
DDR3 RAM2x MT41K256M16TW-107 (Micron) 256Meg x 32 bit
Board Configuration ControllerLCMXO2-7000HC (Lattice)
ADCLTC2320 -16 (Analog Devices)
DACAD5547BRUZ (Analog Devices)
A/D Channels

TXMC639-10R: 8 Differential 16bit A/D Channels

TXMC639-11R: 16 Differential 16bit A/D Channels

Input Configuration per BCC Device:

Input Voltage Ranges:

Differental : ±20.57 V, ±10.28 V or ±5.14 V

(Single-Ended: ±10.28 V, ±5.14 V or ±2.57 V)

All analog inputs are connected via an impedance converter and a second operation amplifier for level adjustment and filtering to the differential ADC inputs.

The -3 dB limit of this input stage is at approx. 8MHz

D/A Channels

TXMC639-10R: 4 Single-Ended 16 Bit D/A Channels

TXMC639-11R: 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.

Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels

32 digital I/O Lines

  • Default configured as 32 ESD-protected TTL lines
  • 16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.
Digital Rear I/O Channels

64 direct FPGA I/O lines to P14 Rear I/O connector

  • Can be used as single-ended or differential I/O
  • FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25

4 MGT line to P16 Rear I/O connector

  • Each line consists of one differential RX and TX pair.
  • Transmission speeds of up to 3.125 Gb/s are possible.
Front I/OFront I/O Samtec – ERF8_050_01_L_D_RA_L_TR
P14 Rear I/O64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1)

Depends on FPGA design

With TXMC639 Board Reference Design / without external load

 typical @ +12 V VPWRtypical @ +5 V VPWR
TXMC639-10R1.1 A2.5 A
TXMC639-11R1.3 A3.3 A
Temperature RangeOperating: – 40 °C to + 85 °C
Storage: – 55 °C to + 125 °C
MTBF 1)157 000 h to 161 000 h
Humidity5% – 95% non-condensing
Weight140 g

1) depends on variant, for further details see User Manual

 

TXMC639-10R

 

8x Analog In, 4x Analog Out, XC7K160T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K160T-2FBG676), 1GB DDR3, 8x Analog In, 4x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

TXMC639-11R

 

16x Analog In, 8x Analog Out, XC7K325T-2FBG676 Kintex™ 7 FPGA

AMD Kintex™ 7 FPGA (XC7K325T-2FBG676), 1GB DDR3, 16x Analog In, 8x Analog Out, 32x digital Front I/O, 64x direct FPGA Rear I/O Lines and 4x MGTs Rear I/O

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet – Link-Here

User Manual – Link-Here

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