<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>PXIe &#8211; ALPHI Technology</title>
	<atom:link href="https://www.alphitech.com/category/pxie/feed/" rel="self" type="application/rss+xml" />
	<link>https://www.alphitech.com</link>
	<description></description>
	<lastBuildDate>Tue, 11 Nov 2025 17:53:13 +0000</lastBuildDate>
	<language>en</language>
	<sy:updatePeriod>
	hourly	</sy:updatePeriod>
	<sy:updateFrequency>
	1	</sy:updateFrequency>
	<generator>https://wordpress.org/?v=7.0</generator>

<image>
	<url>https://www.alphitech.com/wp-content/uploads/2024/10/cropped-AlphiLogo-A-Flavicon-100x100.png</url>
	<title>PXIe &#8211; ALPHI Technology</title>
	<link>https://www.alphitech.com</link>
	<width>32</width>
	<height>32</height>
</image> 
	<item>
		<title>PXIe-XMC-IO</title>
		<link>https://www.alphitech.com/products/pxie/pxie-xmc-io/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 16 Jun 2025 00:29:11 +0000</pubDate>
				<guid isPermaLink="false">https://www.alphitech.com/?post_type=product&#038;p=6761</guid>

					<description><![CDATA[PXIexpress to XMC Non Intelligent Carrier with I/O Interface to Rear I/O]]></description>
										<content:encoded><![CDATA[<ul>
<li>3U PXIe form factor</li>
<li>Single XMC carrier slot</li>
<li>XMC Complies with ANSI/VITA 42.0-2008</li>
<li>PXI Express x8 Lanes</li>
<li>X8 Lanes support up to 8Gbps</li>
<li>PCIeGen-1,2,and3 Capable</li>
<li>Connect User I/O from XMC to Clock and Trigger lane on XJ4</li>
<li>On board XMC JTAG connector</li>
<li>FPGA I/O bank control to PXI interface including Trigger and Clock</li>
</ul>
]]></content:encoded>
					
		
		
			</item>
		<item>
		<title>PXIe-SCC08F</title>
		<link>https://www.alphitech.com/products/pxie/pxie-scc08f/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 17 Mar 2025 23:39:14 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=5860</guid>

					<description><![CDATA[PXIe Octal Serial I/O With 4K FIFO]]></description>
										<content:encoded><![CDATA[<ul>
<li>Eight Z85233 Enhanced Controller</li>
<li>Octal synchronous / Asynchronous serial ports</li>
<li>4K FIFO per Line (TX and RX)</li>
<li>Software selectable RS-232 or RS-422, RS-485 HDLC, SDLC</li>
<li>Individual baud rate generators per port</li>
<li>230 Kbits Async, up to 2 Mbits Sync</li>
<li>Full handshake control line</li>
<li>Software programmable 120 Ohm Termination</li>
<li>Full modem control</li>
<li>Software examples included</li>
</ul>
]]></content:encoded>
					
		
		
			</item>
		<item>
		<title>PXIe-SIP</title>
		<link>https://www.alphitech.com/products/pxie/pxie-sip/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 10 Feb 2025 11:09:02 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4337</guid>

					<description><![CDATA[PXIe Slave Dual Industry Pack Carrier]]></description>
										<content:encoded><![CDATA[<ul class="marker:text-textOff list-disc pl-8">
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Form Factor:</span><span class=""> 3U PXIe format, slave dual industry pack carrier</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Industry Pack Support:</span><span class=""> Supports up to two IP modules, single or double-wide form factor</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">IP Operation Frequency:</span><span class=""> 8 MHz or 32 MHz per slot, software programmable</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Access Method:</span><span class=""> Direct I/O or memory-mapped access from PXIe bus via FPGA x1 PCIe</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Interrupt Support:</span><span class=""> Full interrupt support of host</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">I/O Connectors:</span><span class=""> Front panel I/O connectors for all IPs; rear connector I/O also available</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Maximum I/Os:</span><span class=""> Up to 96 I/Os on one single slot</span></li>
</ul>
]]></content:encoded>
					
		
		
			</item>
		<item>
		<title>PXIe-CIV-PIO-160</title>
		<link>https://www.alphitech.com/products/pxie/pxie-civ-pio-160/</link>
		
		<dc:creator><![CDATA[Ryan]]></dc:creator>
		<pubDate>Mon, 10 Feb 2025 11:06:31 +0000</pubDate>
				<guid isPermaLink="false">https://alphi.expertcreative.com/?post_type=product&#038;p=4335</guid>

					<description><![CDATA[PXIexpress User-Configurable Altera Cyclone IV 64MB Dual Ported DDR Up to 80 RS-422/485 or 160 LVTTL or Combination I/O Sources]]></description>
										<content:encoded><![CDATA[<ul class="marker:text-textOff list-disc pl-8">
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Form Factor:</span><span class=""> 3U PXIe form factor</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Interface:</span><span class=""> PXI Express x1 lane, PCIe Gen-1 capable</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">FPGA:</span><span class=""> User-programmable Altera Cyclone IV FPGA (EP4CE30, 682 pins)</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Memory:</span><span class=""> 64MB dual-ported DDR memory</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">RS-485 Interface:</span><span class=""> 20Mbps RS-485 with logic-selectable 120Ω termination resistor</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">I/O Operations:</span><span class=""> Supports up to 80 RS-422/485 or 160 LVTTL sources, or a combination of both</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">Software-Selectable Features:</span><span class=""> Half or Full Duplex operation</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">JTAG Connector:</span><span class=""> On-board XMC JTAG connector</span></li>
<li><span class="hover:duration-80 duration-800 cursor-pointer underline decoration-textOff/25 decoration-1 underline-offset-[4px] hover:text-super hover:decoration-super/80 hover:underline-offset-[6px] dark:decoration-textOffDark/30 dark:hover:text-superDark dark:hover:decoration-superDark/80 transition-all first:mt-3 motion-reduce:transition-none" data-state="closed">FPGA I/O Bank Control:</span><span class=""> To PXI interface, including Trigger and Clock</span></li>
</ul>
]]></content:encoded>
					
		
		
			</item>
	</channel>
</rss>
